FPGA俄罗斯方块工程详解:Verilog/VHDL与Vivado/ISE版本选型及上板调试
2026/10/14 18:37:18
import{defineConfig}from"vite";import{fileURLToPath,URL}from"node:url";...// https://vite.dev/config/exportdefaultdefineConfig({base:"./",plugins:[...],resolve:{alias:{"@":fileURLToPath(newURL("./src",import.meta.url)),},},});{"compilerOptions":{"paths":{"@/*":["./src/*"]},...}}