企业官网建设流程全解析

一、input_array约束为axis
void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
#pragma HLS INTERFACE axis register both port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

rtl仿真结果：

注意，数组指定axis的时候，不需要指定depth，因为数组默认就已经给定了depth了，数组的大小就是depth，如果是指针变量就不行，指针变量约束为axis,是需要开发者显示的指定detph,否则是死锁的。

二、input_array约束为s_axilite

void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
#pragma HLS INTERFACE s_axilite register port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

需要注意的是，约束为axilte，并不是将其约束为寄存器了，上述代码将其约束为axilite_ram了。

修改代码后：

void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
#pragma HLS INTERFACE s_axilite register depth=4 port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

综合还是生成axilite_bram了。

再次修改：

void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
#pragma HLS ARRAY_PARTITION variable=d_i complete dim=1
#pragma HLS INTERFACE s_axilite register depth=4 port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

三、input_array约束为m_axi------------非常常用

void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
#pragma HLS INTERFACE m_axi port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

上述是数组设计，约束为m_axi的时候，不需要指定depth。如果是指针，需要指定depth.

四、input_array约束为ap_hs

void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
//#pragma HLS INTERFACE m_axi depth=0 port=d_i
#pragma HLS INTERFACE ap_hs port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

五、input_array约束为ap_memory---------非常常用

void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
//#pragma HLS INTERFACE m_axi depth=0 port=d_i
#pragma HLS INTERFACE ap_memory port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

六、input_array约束为bram---------非常常用

void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {
//#pragma HLS INTERFACE m_axi depth=0 port=d_i
#pragma HLS INTERFACE bram port=d_i

int i;

// Breaks FIFO interface d_o[3] = d_i[2];
For_Loop: for (i=0;i<4;i++) {
d_o[i] = d_i[idx[i]];

//d_o[i] = d_i[i];

}

}

七、input_array约束为ap_fifo

八、input_array约束为ap_bus
几乎很少用到，用到再说

九、axilite + ap_memory接口的bram-------非常常用
这个只要你将数组约束为axilite，默认就是生成ap_memory+lite接口的bram资源，注意这里是生成ram了，不只是接口。
这个是生成了实实在在的存储资源，而不是存储资源接口。