verilog HDLBits刷题[Finite State Machines]“Exams/2012 q2b”---Q2b:One-hot FSM equations
2026/8/5 11:36:58 网站建设 项目流程

1、题目

The state diagram for this question is shown again below.

Assume that a one-hot code is used with the state assignmenty[5:0]= 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)

Write a logic expression for the signalY1, which is the input of state flip-flopy[1].

Write a logic expression for the signalY3, which is the input of state flip-flopy[3].

(Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

2、代码

module top_module ( input [5:0] y, input w, output Y1, output Y3 ); parameter A=6'b000001,B=6'b000010,C=6'b000100,D=6'b001000,E=6'b010000,F=6'b100000; reg [5:0]next_state; assign next_state[0]=y[0]&(~w)||y[3]&(~w); assign next_state[1]=y[0]&w; assign next_state[2]=y[1]&w||y[5]&w; assign next_state[3]=y[1]&(~w)||y[2]&(~w)||y[4]&(~w)||y[5]&(~w); assign next_state[4]=y[2]&w||y[4]&w; assign next_state[5]=y[3]&w; assign Y1=next_state[1]; assign Y3=next_state[3]; endmodule

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